PWM resolution bits calculator

Enter the timer clock in hertz, the desired PWM frequency, and an optional integer prescaler. The result includes the prescaled timer tick rate, ideal and usable counts per period, maximum counter value, theoretical fractional-bit resolution, guaranteed whole-bit resolution, achievable frequency, and frequency error. It is intended for quick microcontroller timer planning before register values are selected or firmware is written.

How clock rate and PWM frequency determine resolution

A hardware timer advances once for every timer tick and resets after the programmed period. For an edge-aligned PWM signal, dividing the timer input clock by the prescaler and requested PWM frequency gives the ideal number of counter states in one period. More states let the compare register express more distinct duty-cycle levels. Resolution in bits is therefore the base-two logarithm of the number of states. This calculator floors the ideal count because a timer cannot execute a fractional tick, then floors the logarithm to report complete bits that fit inside the available count. For example, a 72 MHz timer with no prescaler and a 20 kHz target provides 3,600 counts. The theoretical resolution is about 11.81 bits, while 11 complete bits are guaranteed because 2,048 states fit and 4,096 do not. The reported maximum counter value is one less than the count, matching the common convention where a counter runs from zero through ARR or TOP inclusively. This is the fundamental tradeoff in PWM design: raising frequency reduces the number of clock ticks per cycle, while lowering frequency creates more duty steps and finer control.

Reading the calculated timer values

Supply timer_clock_hz as the clock actually feeding the timer peripheral before its own prescaler. Do not automatically use the CPU frequency: microcontrollers often derive timer clocks from peripheral buses, and some clock trees multiply a timer clock when the bus divider is greater than one. pwm_frequency_hz is the desired edge-aligned output rate. The optional prescaler must be a positive integer and defaults to one. The response first shows timer_tick_hz, which is the input clock divided by the prescaler. ideal_counts_per_period preserves the mathematical ratio, while available_counts_per_period is its integer floor. max_counter_value is available counts minus one. resolution_bits is the number of full binary bits represented by those counts; theoretical_resolution_bits retains the fractional logarithm for comparisons. actual_pwm_frequency_hz uses the floored count, so it may be slightly above the target when the ideal period is not an integer. frequency_error_percent quantifies that difference. API automation costs $0.002 per successful item, while invalid inputs are rejected. All calculations are deterministic and use no device database, network lookup, or hidden timer-specific assumptions beyond the stated edge-aligned model.

Applying the result to real microcontroller timers

Treat the result as a feasibility calculation, then compare it with the timer chapter of your microcontroller reference manual. A timer with a 16-bit period register cannot use a maximum counter value above 65,535 even if the clock ratio offers more states; select a larger prescaler or enforce the hardware width separately. Conversely, a result of 10 whole bits does not require the period to be exactly 1,023. It means at least 1,024 distinct positions fit, while a non-power-of-two period may provide additional unevenly described resolution before reaching the next full bit. Center-aligned PWM commonly counts upward and downward, which introduces a factor near two into the frequency equation; adjust the effective target or use the device formula rather than applying this edge-aligned result blindly. Also account for complementary-output dead time, synchronization, repetition counters, and clock changes caused by low-power modes. When exact frequency matters more than maximum duty granularity, test nearby prescaler and period combinations and choose the pair with acceptable frequency error. When smooth LED dimming, motor torque control, or digital power conversion needs finer duty increments, lower the PWM frequency or raise the timer clock. Finally, remember that mathematical resolution describes selectable compare levels, not analog accuracy; switching delays, jitter, driver behavior, and load dynamics can reduce effective performance.